All decade counters are BCD counters.

false

The MOD number of a Johnson counter will always be equal to one-half the number of flip-flops in the counter.

false

All flip-flops in an asynchronous counter change states at the same time.

false

Generally speaking, the synchronous counter requires more circuitry than an asynchronous counter.

true

A J-K flip-flop excitation table lists the present state, the next state, and the J and K levels required to produce each transition.

true

The term synchronous refers to events that do not occur at the same time.

false

Another term used to describe up/down counters is bidirectional.

true

The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.

true

Once an up/down counter begins its count sequence, it cannot be reversed.

false

The terminal marked A on the CTR block in Figure 7-1 is the SET terminal.

false

Most sequential circuits contain a combinational logic section and a memory section.

true

A counter whose MOD = 2N will always have a 50% duty cycle.

true

Basic counters can be cascaded in parallel to increase the number of data bits that the counter can handle.

false

Counters are generally decoded in order to determine their count state.

true

In many cases, counters must be strobed in order to eliminate glitches.

true

Shift registers are used to store and transfer data.

true

A parallel in/serial out shift register enters all data bits simultaneously and transfers them out one bit at a time.

true

A serial in/serial out shift register transfers data from one line of a parallel bus to another line one bit at a time.

false

The serial in/parallel out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.

false

Bidirectional shift registers can shift data either right or left.

true

A reliable method for eliminating decoder spikes is to use strobing.

true

An effective time delay device can be constructed by using the propagation delay characteristic of parallel shift registers.

false

Shift register counters use logic functions to reset the registers when the desired count is reached.

false

Parallel in/parallel out registers have parallel input and output busses.

true

In a full-featured counter in HDL, the concept of rolling over simply means the count sequence has reached its limit and must start over at the beginning of the sequence.

true

One characteristic of a ring counter is that the modulus is equal to the number of flip-flops in the register and, consequently, there are never any unused or invalid states.

false

The concept of a counter to implement a digital one-shot using HDL is not used.

false

In VHDL, when we want to remember a value it must be stored in a VARIABLE.

true