front 1 All decade counters are BCD counters. | back 1 false |
front 2 The MOD number of a Johnson counter will always be equal to one-half the number of flip-flops in the counter. | back 2 false |
front 3 All flip-flops in an asynchronous counter change states at the same time. | back 3 false |
front 4 Generally speaking, the synchronous counter requires more circuitry than an asynchronous counter. | back 4 true |
front 5 A J-K flip-flop excitation table lists the present state, the next state, and the J and K levels required to produce each transition. | back 5 true |
front 6 The term synchronous refers to events that do not occur at the same time. | back 6 false |
front 7 Another term used to describe up/down counters is bidirectional. | back 7 true |
front 8 The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time. | back 8 true |
front 9 Once an up/down counter begins its count sequence, it cannot be reversed. | back 9 false |
front 10 The terminal marked A on the CTR block in Figure 7-1 is the SET terminal. | back 10 false |
front 11 Most sequential circuits contain a combinational logic section and a memory section. | back 11 true |
front 12 A counter whose MOD = 2N will always have a 50% duty cycle. | back 12 true |
front 13 Basic counters can be cascaded in parallel to increase the number of data bits that the counter can handle. | back 13 false |
front 14 Counters are generally decoded in order to determine their count state. | back 14 true |
front 15 In many cases, counters must be strobed in order to eliminate glitches. | back 15 true |
front 16 Shift registers are used to store and transfer data. | back 16 true |
front 17 A parallel in/serial out shift register enters all data bits simultaneously and transfers them out one bit at a time. | back 17 true |
front 18 A serial in/serial out shift register transfers data from one line of a parallel bus to another line one bit at a time. | back 18 false |
front 19 The serial in/parallel out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line. | back 19 false |
front 20 Bidirectional shift registers can shift data either right or left. | back 20 true |
front 21 A reliable method for eliminating decoder spikes is to use strobing. | back 21 true |
front 22 An effective time delay device can be constructed by using the propagation delay characteristic of parallel shift registers. | back 22 false |
front 23 Shift register counters use logic functions to reset the registers when the desired count is reached. | back 23 false |
front 24 Parallel in/parallel out registers have parallel input and output busses. | back 24 true |
front 25 In a full-featured counter in HDL, the concept of rolling over simply means the count sequence has reached its limit and must start over at the beginning of the sequence. | back 25 true |
front 26 One characteristic of a ring counter is that the modulus is equal to the number of flip-flops in the register and, consequently, there are never any unused or invalid states. | back 26 false |
front 27 The concept of a counter to implement a digital one-shot using HDL is not used. | back 27 false |
front 28 In VHDL, when we want to remember a value it must be stored in a VARIABLE. | back 28 true |