A "D" flip-flop with a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
CLK = PGT, D = 1
A 1.5 MHZ clock signal is applied to an eight flip-flop binary counter. Which of the following indicates the proper MOD number, maximum number of counts, maximum count, and output frequency of the circuit?
MOD 256, 256 counts, 255 maximum count, and 5,859.38 Hz
To find the Output F = Input Signal/Mod #
A D-type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.
False
A NAND latch has outputs of Q = 1 and = 0. What effect will applying a LOW to the CLEAR input have on the latch?
It will have no effect because a HIGH input is required to change NAND latch states
A flip-flop is always SET by the positive-going transition that occurs when power is first applied.
True
A negative-edge-triggered J-K flip-flop is presently in the CLEAR state. Which of the following input conditions will cause it to change states?
CLK = PGT, J = 1, and K = 0
A one-shot has a stable output state that is essentially interrupted by the trigger input. Once interrupted, the output goes to the opposite state for a specific amount of time.
True
A primary difference between a clocked J-K flip-flop and a clocked S-C flip-flop is the J-K's ability to:
toggle or change states when J = 1, K = 1, and a clock transition occurs.